Memory components, such as DRAMS (Dynamic Random Access Memory), are electronic storage mechanisms that are used to store data for computing systems. DRAMs are widely used in digital electronics where low-cost and high-capacity memory is required. For example, a typical application for DRAM products is the main memory for a computer system. There are many types of DRAMs that are used in modern systems, such as for example, DDR (double data rate) systems.
In general, DDR systems transmit data on both edges of a clock/strobe, where the memory system sends and/or receives a data edge aligned with a strobe. However, due to various electrical differences within the memory itself or other components which interact with the memory, the data and strobe might arrive at the memory with varying skews.
The issue addressed by the present disclosure is that periodic training is often needed to ensure that the DDR memory has its strobe properly aligned with the data edges. This is because over time, drifts may occur between the alignment of the clock strobes and the data edges. Such misalignments may cause incorrect data to be stored and/or read by the memory product, unless such skews are accounted for by proper adjustment of delay components.
DDR systems provide the ability to train for the best clock strobe and data settings. To perform this type of training, the delay of the data is varied relative to the strobe (or vice versa) until the proper calibration is achieved. An iterative approach is often taken to perform this training process, where either the clock strobe and/or data position is repositioned by a small “step” through application of instructions to applicable delay components. These incremental steps are taken until the training process identifies the correct adjustments that need to be taken to optimize the setting of the various clock strobe and data components.
The problem is that, depending upon the amount of drift that has occurred, a significant amount of these incremental training steps may need to be taken to accomplish the training process. This causes a period of delay to occur before the memory product can be usefully operated. This delay may not be a significant problem during, for example, the initialization of the memory component upon startup. However, consider when the system that includes the memory component is in the midst of user operation when the training occurs. In this situation, a significant amount of delay in responsiveness due to memory re-training may cause unwanted stalling of the main application that relies upon the memory component, thereby creating perceptible delays and/or possible glitches in the operation of the system.
Therefore, there is a need for an improved approach to implement training for memory technologies that addresses these and other problems of conventional systems.